Physical Design Engineer

Profile

Cirrus Logic is looking for an expert Physical Design Engineer to join its Implementation team. You will be part of a team working on implementing industry-leading mixed-signal SoC for consumer mobile audio markets. This role would suit a candidate with an ability to work independently and as part of a wider design team.

Responsibilities

We will incorporate you on a team that is involved in all aspects of physical implementation from RTL to GDSII

Perform RTL synthesis and scan stitching

Applying deep knowledge of timing optimization and experience with ECO generation to analyze and fix timing issues in 40nm, 28nm and below

You will be defining and debugging Timing Constraints and performing STA using industry-standard STA engines and a deep understanding of timing correlation to achieve timing closure.

Build timing constraints for the entire chip in a team environment

Knowledge of automating and advancing flows using proficiency in Perl/Tcl scripting

Analyze power constraints and chip floor plan

You will analyze clock distribution on full-chip assembly

Physical design-related flow development, tool evaluation, flow automation, QA and improvement.

You will develop Placement & Route structures for a complete ASIC design

Build Static Timing Analysis, timing closure, ECO and tape-out

IR Drop analysis and improvement on almost all designs

Required

Skills and Qualifications

Bachelor's or Master's in Electrical Engineering and 8 years of industry experience in a Logic design or Physical Design position

Strong solid understanding of RTL design, and the ideal candidate should be familiar with RTL compiler/Design Compiler, ICC/SOC Encounter

You should have Primetime, Conformal LEC, and ATPG

You will also have a solid understanding of scan insertion, and ATPG

Good communication and collaboration skills

Preferred

Skills and Qualifications

We will look to have you be involved in design/architecture reviews which will help add to the overall progress and improvement of the team.

Experience with multiple clock domains

Experience defining physical design methodologies and flow automation

Ability to perform debug/analysis skills for designs, library, and technology files

Ability to provide mentorship and guidance to junior engineers and be a very effective teammate

This position is located in Austin, TX

This hybrid on-site position will follow a 2 day in-office work schedule, with in-office days based on business needs and team preference. You must be based within commutable distance of the work location listed on the job posting or willing to relocate before beginning employment with Cirrus Logic.

Cirrus Logic is an Equal Opportunity/Affirmative Action Employer. We strive to select the best-qualified applicant for any opening and to reward employees based on their skills, experience, and performance. We do not discriminate based on race, national origin, pregnancy status, marital status, gender, age, religion, physical or mental disability, medical condition, veteran status, sexual orientation, genetic information, or any other characteristic protected by law.

#LI-DB1

#LI-Hybrid

Apply

Company info

Cirrus Logic, Inc.
Website : http://www.cirrus.com